http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-201340221-A

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filingDate 2012-03-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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publicationDate 2013-10-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber TW-201340221-A
titleOfInvention Method for manufacturing wafer level semiconductor package and method for manufacturing wafer level package substrate
abstract A method for fabricating a wafer-level semiconductor package, comprising: forming a first dielectric layer on a carrier plate and exposing a portion of the carrier plate; forming a circuit layer on the first dielectric layer and the first opening; forming a second dielectric layer on the first dielectric layer and the circuit layer, and a portion of the wiring layer is exposed; a conductive bump is formed in the second opening; a semiconductor component is bonded to the conductive bump; and the package is encapsulated Overlying the semiconductor component; and removing the carrier to expose the wiring layer. By first fabricating the circuit layer, after the yield of the circuit layer is to be detected, the semiconductor component is placed to avoid invalidating the good semiconductor component and the package, thereby saving manufacturing cost and improving yield. The invention provides a method for manufacturing the wafer level package substrate.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I802181-B
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priorityDate 2012-03-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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