| abstract |
A semiconductor device has a semiconductor die having a plurality of bumps formed over a surface of the semiconductor die. The bumps can include a fusible portion and non-fusible portion. Conductive traces are formed over the substrate with interconnect sites having an exposed sidewall and sized according to a design rule defined by SRO + 2*SRR - 2X, where SRO is an opening over the interconnect site, SRR is a registration for the manufacturing process, and X is a function of a thickness of the exposed sidewall of the contact pad. The bumps are misaligned with the interconnect sites by a maximum distance of X which ranges from 5 to 20 microns. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate. |