Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-165 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78642 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-027 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7827 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3065 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-308 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-304 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-30604 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823431 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31144 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66666 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31111 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31116 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02126 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-306 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3065 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-027 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-311 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-304 |
filingDate |
2019-10-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dc480c10b4fd6bf1fcbff44694d8f89a http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bc867deb53059ce1795c7cc2a25c3f6a http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8d7c48034d704c1ebc8bf53b8898edb3 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_29b5da81252ad42eb7a661d4ca654e05 |
publicationDate |
2020-06-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
KR-20200066553-A |
titleOfInvention |
Semiconductor arrangement and method for making |
abstract |
A method for manufacturing a semiconductor device includes performing a first etch of the semiconductor structure to expose a first portion of the sidewall of the first layer adjacent the semiconductor structure. The first etch forms a first protective layer on a first portion of the sidewall of the first layer, the first protective layer formed from a first accumulation of byproduct materials formed from an etchant of the first etch that interacts with the semiconductor structure do. The method includes performing a first flash to remove at least a portion of the first protective layer. |
priorityDate |
2018-11-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |