http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20200007643-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0886 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7827 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7831 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823431 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66666 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3086 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823456 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-732 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823487 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42376 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823468 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42392 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-732 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 |
| filingDate | 2019-04-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1027d2950847620d4ec2effb9cfe5539 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_391adf31d6aa1a067e1e82cdc61b6d93 |
| publicationDate | 2020-01-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20200007643-A |
| titleOfInvention | Semiconductor device and method for fabricating the same |
| abstract | A semiconductor device is provided. A semiconductor package is a semiconductor device including at least two vertical field effect transistors (VFETs) having different gate lengths, the semiconductor substrate including a top surface and a bottom surface, the top surface having a first height relative to the bottom surface of the semiconductor substrate. A first top surface positioned at a second top surface and a second top surface positioned at a second height with respect to a bottom surface of the semiconductor substrate, wherein the first height is different from the second height and protrudes from the first top surface of the semiconductor substrate; The second fin protruding from the second top surface of the substrate, the top of the first fin and the top of the second fin are at the same height, wherein the first gate structure and the first gate structure on the first top surface of the semiconductor substrate are formed by A first gate conductive layer on the first gate insulating layer and the first gate insulating layer, wherein the first gate structure surrounds the first fin along a top surface of the semiconductor substrate at a first thickness And a second gate structure on a second top surface of the semiconductor substrate, wherein the second gate structure includes a second gate insulating layer and a second gate conductive layer on the second gate insulating layer, and the second gate structure comprises: a second gate structure; The two fins are surrounded by a second thickness along the top surface of the substrate of the semiconductor, the first thickness and the second thickness including different ones. |
| priorityDate | 2018-07-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 32.