| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823864 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823437
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7833
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02164
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28008
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42364
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0217
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0332
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6659
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31144
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28247
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823468 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate |
2016-10-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_648b7e03d52ce6e763b6d3b7cc55f924
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1b8fbfaa4b350f6f72029b9841fafc8b |
| publicationDate |
2017-06-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-20170063356-A |
| titleOfInvention |
Spacer structure and manufacturing method thereof |
| abstract |
A spacer structure and a method of manufacturing the spacer structure are provided. The method includes the following steps. A first conductive structure and a second conductive structure are formed on a substrate. A dielectric layer is formed to cover the first conductive structure and the second conductive structure. A hard mask layer is formed on the dielectric layer. The hardmask layer covering the dielectric layer on the first conductive structure and the hardmask layer including an opening exposing the dielectric layer on the second conductive structure. The dielectric layer exposed by the hard mask layer is etched to reduce the thickness of the dielectric layer. The hard mask layer is removed. The dielectric layer is etched to form a first main spacer on the sidewalls of the first conductive structure and a second main spacer on the sidewalls of the second conductive structure. The first width of the first main spacer is larger than the second width of the second main spacer. |
| priorityDate |
2015-11-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |