| abstract |
Thereby improving the performance of the semiconductor device. The semiconductor device includes an SOI substrate SB1 and a MISFET Q1 formed on the SOI substrate SB1. The SOI substrate SB1 includes a substrate SS1, a ground plane GP formed on the substrate SS1, a BOX layer 3 formed on the ground plane region GP and an SOI layer 3 formed on the BOX layer 3. [ (4). The base body SS1 is made of silicon, and the ground plane region GP includes a semiconductor region 1 made of silicon carbide. |