http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20070101435-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09F3-205 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09F3-0295 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09F19-228 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-335 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-768 |
| filingDate | 2006-04-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1f2fa29283b3d21e61ae1bfe4e41bb43 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_120c477809a92e7f77db0fb6f8231be7 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6cfd24b7240fad40f91a706518c737f9 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_732cfd96fc57c94cdfb3044df100fba3 |
| publicationDate | 2007-10-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20070101435-A |
| titleOfInvention | Semiconductor device and manufacturing method thereof |
| abstract | A method of manufacturing a MOS field effect transistor having a nanowire-shaped channel is disclosed. The present invention sequentially forms a sacrificial layer and a semiconductor layer having an etching selectivity with respect to each other on a semiconductor substrate, and then forms a first mask layer pattern extending in a first direction on the semiconductor layer and using the same as an etching mask. As a result, recess regions in which the sacrificial layer is exposed on both sides of the first mask layer pattern are formed. Subsequently, after forming a first mask layer pattern that is smaller than the width of the first mask layer pattern, a first buried material layer is formed on the entire surface, and extends in a second direction perpendicular to the first direction, wherein the reduction is performed in the middle. After forming a pair of spaced apart hard mask layer patterns exposing the top surface of the first mask layer pattern, it is used as an etching mask to form a first opening through which the sacrificial layer is exposed. Subsequently, the first buried material layer is etched using the hard mask layer pattern as an etching mask to form a second opening through which the sacrificial layer is exposed, and then the exposed sacrificial layer is removed to expose the periphery of the semiconductor layer. Subsequently, after the second buried material layer is formed on the entire surface of the semiconductor substrate, a second buried material layer remaining between the semiconductor layer and the semiconductor substrate is formed by a surface planarization or etching process, and the semiconductor layer is A gate insulating layer and a gate electrode layer are formed to be spaced apart from the remaining second buried material layer and surround the exposed semiconductor layer. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20160024058-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9508832-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20150039488-A |
| priorityDate | 2006-04-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 31.