http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20050063898-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0727 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66659 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823412 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66621 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823437 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823481 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate | 2003-12-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_723fdce88478250580157d03543f6d52 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5ab4e9b538229f7084d9b90a4a73794e http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8544119a3bbe72bd585fde2ca52c756d http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_92180d94f359c5196a4a2a5fb8935975 |
| publicationDate | 2005-06-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20050063898-A |
| titleOfInvention | Method for manufacturing recess type mos transistor and structure at the same |
| abstract | The present invention discloses a method of manufacturing a recess-type MOS transistor which can improve refresh characteristics. The method includes ion implanting a first conductive impurity into an active region of a semiconductor substrate to form a channel impurity region, and a second conductive impurity opposite to the first conductive impurity in the active region where the channel impurity region is formed; Alternately implanting the first conductive impurities and sequentially forming first to third impurity regions having a double diode structure from the channel impurity regions, and forming the first to third impurity regions in the active region. Forming a trench that penetrates and has a bottom in the channel impurity region, forming a gate stack through a gate insulating film in a gate region on the semiconductor substrate on which the trench is formed, and a source region of the semiconductor substrate on which the gate stack is formed; Selectively ion implanting a first conductive impurity into the source region Forming a fourth impurity region having a boundary at the channel impurity region, forming a spacer on a sidewall of the gate stack, and using the spacer and the gate stack as an ion implantation mask to form the second conductive impurity. And implanting ions into the source / drain regions to form a fifth impurity region. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20200074756-A |
| priorityDate | 2003-12-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 39.