| abstract |
The present invention provides a low cost and high performance functional circuit by shortening the time required for the logic synthesis and the repetition of layout wiring in the functional circuit design. A standard cell used for logic synthesis and layout wiring is composed of an output logic circuit and an input logic circuit, to increase the driving capability of the output logic circuit, and to reduce the gate input capacity of the input logic circuit. By setting it as the standard cell of such a structure, the ratio which the gate delay occupies among the delay time in a functional circuit can be made relatively high. Therefore, if the gate delay of each standard cell is estimated with high accuracy, the operating frequency can be obtained with high accuracy at the time of logic synthesis, even if the wiring capacitance after the layout wiring is not accurately estimated in advance. That is, the reliability of the logic synthesis result is improved, and the logic composition and the automatic arrangement wiring need not be repeated, and the design period can be shortened. |