http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20040051575-A

Outgoing Links

Predicate Object
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823487
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-0963
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-0948
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-0948
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-822
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-82
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-118
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-096
filingDate 2002-02-07-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationDate 2004-06-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber KR-20040051575-A
titleOfInvention Monotonic dynamic-static pseudo-NMOS logic circuit and method of forming a logic gate array
abstract The disclosed invention relates to a monotonic dynamic-static pseudo-NMOS logic circuit. More specifically, a dynamic logic circuit comprising a clock input and an output configured to be high transition when a low clock signal is provided to the clock input; And a static logic circuit comprising a clock bar input and an output configured to transition low when a high value of the number of clock inputs is provided to the clock bar input. The logic gate array is constructed by connecting a plurality of vertical ultra thin transistors to each other.
priorityDate 2001-02-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

Predicate Subject
isDiscussedBy http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID5461123
http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419559541

Total number of triples: 21.