| abstract |
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer-level stacked chip package and a method of manufacturing the same. In order to implement a stacked chip package in which a semiconductor device manufactured at a wafer level is stacked in three dimensions, a cultivation layer having a wiring layer for rearranging chip pads of the semiconductor device is formed. The semiconductor device fabricated at the wafer level on the line substrate is laminated in three dimensions through a filling layer, and the electrical connection between the semiconductor devices stacked as a conductive filler formed in the semiconductor device is realized, and then the semiconductor device stacked on the redistribution substrate. By separating them, multiple stacked chip packages can be obtained at the wafer level. At this time, the semiconductor device stacked on the redistribution substrate can improve the yield of the laminated chip package by using only the semiconductor device determined as good among semiconductor devices manufactured at the wafer level. As the filling layer compensates for the electrical property degradation due to the thin thickness of the polymer layer of the stacked semiconductor devices, the electrical property may be suppressed from falling. A heat dissipation metal layer is interposed between the stacked semiconductor devices, and a metal cover is formed on the outside of the stacked semiconductor devices, thereby effectively dissipating heat generated from the stacked chip package to the outside, thereby improving electrical characteristics. The heat dissipation metal layer may be used as the ground layer to further improve electrical characteristics of the multilayer chip package. In addition, since the semiconductor device is stacked on the redistribution board to implement the stacked chip package, the fan in and the fan out may be implemented depending on how the wiring layer formed on the redistribution board is formed. |