http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20020054662-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1a492183be65153abfa7dec00d51c816 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-7685 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76807 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-2885 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3212 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02068 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76877 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76873 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-7684 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 |
| filingDate | 2000-12-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_11347f77f817d90392121ff34ff9a49c |
| publicationDate | 2002-07-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20020054662-A |
| titleOfInvention | A method for forming a metal line of a semiconductor device |
| abstract | BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device, and comprises a via exposing a first metal wiring in order to easily form a metal wiring by performing a metal wiring forming process by a dual damascene method using copper. An interlayer insulating film having a trench formed in a region defined as a contact hole and a second metal wiring is formed on the semiconductor substrate, the first metal wiring is cleaned, and a barrier metal layer is formed on the entire surface including the via contact hole. And forming a copper seed layer on the barrier metal layer, and depositing a copper layer on the copper seed layer by electroplating to fill the via contact hole and a trench, and planarize by electropolishing the copper layer. After exposing the barrier metal layer, the barrier metal layer is CMP to form a planarized second metal interconnection and the second metal interconnection. And a metal wiring having a sufficient operating characteristics in high integration of semiconductor elements in the step of forming the entire surface of the upper capping layer to form, including a technique that allows the speed of the semiconductor device. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100413632-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100467803-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100906307-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7544601-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100712818-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-101239430-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100729126-B1 |
| priorityDate | 2000-12-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 40.