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filingDate 2016-11-23-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2022-11-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationDate 2022-11-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber KR-102467944-B1
titleOfInvention Method of forming internal dielectric spacers for horizontal nanosheet FET architectures
abstract A method of forming a nanosheet stack of a semiconductor device is provided. A method of forming a nanosheet stack of a semiconductor device includes forming a stack including a plurality of sacrificial layers including an upper sacrificial layer and a lower sacrificial layer and at least one channel layer on a lower layer film, and including at least one source and Forming a drain trench region, exposing the surface of the sacrificial layer and the surface of at least one channel layer, and under wet oxygen, or ozone and UV conditions, the exposed surface and exposure of the sacrificial layer oxidizing the surface of at least one channel layer, wherein the lower sacrificial layer is in contact with the lower layer film, the channel layer is in contact with at least one sacrificial layer, the sacrificial layer is formed of SiGe, and the at least one channel layer is Si form with
priorityDate 2016-05-23-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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