http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-102207028-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78618 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42384 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78621 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-247 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7869 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41733 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78606 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78636 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate | 2013-11-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2021-01-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2021-01-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-102207028-B1 |
| titleOfInvention | Semiconductor device |
| abstract | The present invention provides a semiconductor device capable of miniaturization or high integration. Alternatively, it imparts good electrical properties to a semiconductor device in which an oxide semiconductor is used. Alternatively, a highly reliable semiconductor device is provided by suppressing fluctuations in electrical characteristics of a semiconductor device using an oxide semiconductor. The semiconductor device includes an island-shaped oxide semiconductor layer provided on an insulating surface, an insulating layer surrounding a side surface of the oxide semiconductor layer, a source electrode layer and a drain electrode layer in contact with the upper surface of the oxide semiconductor layer and the upper surface of the insulating layer, and an oxide semiconductor layer. And a gate electrode layer provided so as to overlap with and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode layer, and the source electrode layer and the drain electrode layer are provided above the upper surface of the oxide semiconductor layer, and the upper surface of the insulating layer is planarized. |
| priorityDate | 2012-12-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 80.