| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0207
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76895
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823437 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0692
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0611
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4958
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823475
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76832
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0886
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823431
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-485
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4236 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-49
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06 |
| filingDate |
2016-11-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2018-10-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2018-10-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-101893656-B1 |
| titleOfInvention |
Structure and method for semiconductor device |
| abstract |
A method of forming a semiconductor structure according to the present invention includes the following operations. The gate structure is disposed over the first active region, the second active region, and the non-active region of the substrate of the semiconductor structure. The first active area and the second active area are separated by a non-active area. The contacts are disposed over the first and second active areas. At least one gate via is disposed over the first active region or the second active region. At least one gate via is electrically connected to the gate structure. At least one local interconnect is selectively disposed over the non-active region to connect at least one of the contacts on the first active region to at least one of the contacts on the second active region. |
| priorityDate |
2016-05-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |