http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-101153167-B1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_88e64e89c1d5154f303de637c7750eda |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2863 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2884 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2896 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2886 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-26 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R1-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-66 |
| filingDate | 2011-11-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2012-06-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1b82d8e17bdc531a839d353e27b1ae65 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5345bac0c79628c024b374a99aab7a2f http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1ce1405ff93d17d3afd578a9a74589ee http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f2573e10db4cc8f6d9daf78517847e4a http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_93e5111792446c96da622520834290cd http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e05fc32defa0194af170c4ad8fa8a1f9 |
| publicationDate | 2012-06-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-101153167-B1 |
| titleOfInvention | Chip guide unit for test socket |
| abstract | A chip guide unit for a test socket is disclosed. The test guide chip guide unit may include a plurality of contact holes into which the test chip is seated and the test pin is inserted such that the test pin is in contact with the pad of the seated test chip. The chip guide unit for the test socket may be formed on a first insulating layer in which a plurality of first holes having the same central axis as the contact holes are formed, an upper surface of the first insulating layer, and corresponding to one of the first holes. The second chip having the same central axis as the first hole is formed on the metal layer and the upper surface of the metal layer, the test chip is seated, the same as the first hole and the second hole having the same central axis And a second insulating layer having a plurality of third holes having a central axis, wherein the metal layer surrounds each of the second holes to insulate a metal part surrounding each of the second holes. Insulation holes penetrating the upper surface and the lower surface may be formed along the edge of the. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-106370892-A |
| priorityDate | 2011-11-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 26.