http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100998948-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823437 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66621 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate | 2008-07-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2010-12-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2010-12-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100998948-B1 |
| titleOfInvention | Method for manufacturing semiconductor device having recess gate |
| abstract | The present invention is to provide a method of manufacturing a semiconductor device having a recess gate that can prevent a short circuit between the gate pattern and the landing plug contact, the present invention comprises the steps of forming an isolation region on the substrate to define an active region; Forming a mask pattern on the substrate of the active region, the mask pattern having an opening having a first width for opening a recess pattern formation region and an opening having a second width less than the first width and exposing the device isolation layer; Forming an etch protection layer on the mask pattern along a step; Forming a recess pattern by etching the substrate using the etching protection layer and the mask pattern as an etch barrier; Removing the etching protection layer and the mask pattern; Filling the recess pattern and forming a gate pattern protruding above the substrate, wherein the etch protection layer fills between mask patterns having the openings of the second width, and protects the device isolation layer when the recess pattern is formed. By preventing the loss and preventing the recess pattern from being formed in the device isolation layer, there is an effect of preventing the occurrence of a short circuit between the gate pattern on the device isolation layer and the landing plug contact during the subsequent cleaning process.n n n n Recess, photoresist pattern, short circuit |
| priorityDate | 2008-07-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 19.