http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100951227-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-513 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-517 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4966 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823857 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28079 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-495 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L31-113 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-335 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-51 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-49 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L31-119 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L31-113 |
| filingDate | 2005-03-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2010-04-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2010-04-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100951227-B1 |
| titleOfInvention | Selective Implementation of Barrier Layers for Controlling Threshold Voltages in CMOS Devices with High-K dielectrics |
| abstract | A method of forming a CMOS structure with improved threshold voltage and flat band voltage stability and a device produced thereby are disclosed. The method includes providing a semiconductor substrate having an nFET region and a pFET region, removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region, and drawing at least one gate stack in the pFET region and in the nFET region. Providing at least one gate stack. The insulating interlayer can be AlN or AlO x N y . The high dielectric constant (k) dielectric may be HfO 2 , hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by wet etching with HCl / H 2 O 2 peroxide solution.n n n n CMOS, high dielectric constant, threshold voltage, isolated interlayer |
| priorityDate | 2004-06-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 43.