| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-13062 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823487
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66893
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-098
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42392
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7827
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66742
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78642
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-8083
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66666
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66909 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-095
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-808
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-098
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8232
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-80
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-337 |
| filingDate |
2009-07-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2009-12-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2009-12-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-100929335-B1 |
| titleOfInvention |
A vertical replacement-gate junction field-effect transistor |
| abstract |
An architecture for creating vertical JFETs. In general, integrated circuit structures include a semiconductor region having a major surface formed along a plane, and a first source / drain doped region formed thereon. A second doped region that forms a channel of a different conductivity type than the first region is disposed on the first region. The third doped region is formed on the second doped region having a conductivity type opposite to the second doped region, and forms a source / drain region. A gate is formed on the channel to form a vertical JFET.n n n In a related method of manufacturing a semiconductor device, a first source / drain region is formed in a semiconductor layer. A field effect transistor gate region comprising channel and gate electrodes is formed on the first source / drain region. A second source / drain region is then formed on the channel with the appropriate conductivity type. |
| priorityDate |
2001-09-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |