| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-03 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-40114
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-47
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-105
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32137 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-105
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3213
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-52
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247 |
| filingDate |
2003-09-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2006-02-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2006-02-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-100555366-B1 |
| titleOfInvention |
Polysilicon Etching Method and Semiconductor Memory Manufacturing Method |
| abstract |
A polysilicon layer that maintains the anisotropic shape of the polysilicon layer and is able to completely remove the polysilicon residues remaining on the stepped sidewalls covered with the polysilicon layer after the polysilicon layer is patterned, leaving the underlying insulating film unetched Silicon etching methods are provided. After the polysilicon layer is deposited on one main surface of the substrate, the step is covered, and a resist layer is formed on the polysilicon layer on the step. By using the resist layer as a mask, a plasma etching process is performed to pattern the polysilicon layer to form a gate electrode polysilicon layer. In the first step, the polysilicon layer is etched using HBr and Cl 2 until the polysilicon spacer residues appear on the sidewalls of the step, and in the second step the polysilicon residues are HBr at a pressure of 5 mTorr to 10 mTorr. Is removed using. |
| priorityDate |
2002-09-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |