| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c5520dd38cc403678d9f91e0b0ee95fb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0f4246e8fcebf17c365aced017a04c61 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66765
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4908
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28008
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28158
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66757 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G02F1-136
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G02F1-1368
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-49
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 |
| filingDate |
1995-12-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
1999-11-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b7b7118596e0827277be1aa0b1050356
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5ec11018298fea6a673b1418b6f3018b |
| publicationDate |
1999-11-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-100231508-B1 |
| titleOfInvention |
Thin Film Transistor and Manufacturing Method Thereof |
| abstract |
The thin film transistor of the present invention includes an ONO insulator structure interposed between a gate electrode and a polycrystalline silicon semiconductor layer, wherein the polycrystalline silicon semiconductor layer includes a source region, a drain region, and a channel between the source region and the drain region. Wherein the ONO insulator structure includes an interfacial oxide layer in contact with the polycrystalline silicon semiconductor layer, a cap oxide layer in contact with the gate electrode, and a nitride layer interposed between the interfacial oxide layer and the cap oxide layer, wherein the nitride layer is the interface. Thinner than the oxide layer and the cap oxide layer is characterized in that the thicker than the interfacial oxide layer. |
| priorityDate |
1995-02-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |