http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H09252124-A

Outgoing Links

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0950e9df7f0e1b73efee1bda859951ad
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
filingDate 1996-03-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_da29e58da46ea75d3b421dc54b0971fd
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_276008c704c184d58512b332d6781d2f
publicationDate 1997-09-22-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H09252124-A
titleOfInvention Semiconductor device and manufacturing method thereof
abstract (57) Abstract: A high-speed semiconductor device having no malfunction is provided. A semiconductor substrate having a gate insulating film formed on the surface thereof, a gate electrode formed on the surface of the gate insulating film, and a surface region of the semiconductor substrate sandwiching the gate electrode from both sides. Formed impurity regions 7a, 7 b, 10a, 10b, the first sidewall insulating film 9 formed on the sidewall of the gate electrode, the interlayer insulating film 14 formed on the surface of the gate electrode and provided with the sidewall, and the interlayer insulating film Second sidewall insulating film 17 formed on the sidewall of the film And a wiring formed in the opening 15 surrounded by the second sidewall insulating film and connected to the impurity region.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2007048837-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-5062166-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100475118-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-4550685-B2
priorityDate 1996-03-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

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Total number of triples: 19.