http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H09205152-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_294881271413951a95f284b588a68e66 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-665 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28052 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28061 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823842 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-06 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate | 1996-01-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cea61ec0fb20555378659003a15c409b |
| publicationDate | 1997-08-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-H09205152-A |
| titleOfInvention | CMOS semiconductor device having two-layer gate electrode structure and manufacturing method thereof |
| abstract | (57) Abstract: It is possible to prevent interdiffusion of introduced impurities through an upper silicide electrode layer. A p-type impurity having a p-type impurity concentration approximately equal to that of a lower gate electrode layer and an n-type impurity having a similar n-type impurity concentration are introduced into a silicide electrode layer. There is. This allows the pMOS side and the nMO On both sides of S, the introduced impurity concentration of the gate electrode layer 16 is balanced on both sides of the connection surface of both sides, thermal diffusion due to subsequent heat treatment is prevented, and the problem of mutual diffusion can be fundamentally solved. The present invention is suitable for the salicide process. Even when the silicide electrode layer 18 is simultaneously formed on an extremely thin source or drain region, since the impurity concentration of the silicide electrode layer 18 is high in advance, it may happen that the underlying impurities are absorbed and the contact resistance is deteriorated. Because there is no. As a result, the salicide process can be easily applied to submicron devices. In the manufacturing method of the present invention, the silicide electrode layer 18 is formed by the CVD method or the sputtering method, and impurities are introduced during the film formation. Therefore, it is not necessary to provide a step for introducing impurities, which is preferable. |
| priorityDate | 1996-01-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 38.