| abstract |
A wiring width is reduced in consideration of electromigration resistance, a width of an input / output cell region is reduced to increase the number of input / output cell regions, and a large number of pins are achieved. An input / output cell region 13 for forming an input / output circuit 15 has a plurality of nMOS transistors 16 and 17 and pMOS transistors 18 and 19. nMOS The transistor 16 constitutes the transistor group 21, the pMOS transistor 18 constitutes the transistor group 22, the nMOS transistor 17 constitutes the transistor group 23, and the pMOS transistor 19 constitutes the transistor group 24. The transistor groups 21 to 24 are arranged side by side in a direction orthogonal to the circumferential direction of the semiconductor chip. The transistor group 21 to 24 is connected alternately to the high-potential power supply V DD and the low-potential power supply V SS in accordance with the arrangement order, the transistor group 21 to 24 is connected to the external pad 14 by a common aluminum wiring 35. |