| abstract |
(57) Abstract: To obtain a larger capacitor capacitance for a predetermined area. Generally speaking, the present invention utilizes a dry plasma etching method such as electron cyclotron resonance (ECR) to create graded sidewalls in a DRAM storage cell. The rounded corners of the lower electrode made by this method allow the high-grade dielectric material to be deposited without substantial cracking, and the uniformity in making this high-grade dielectric layer also allows for electrostatic capacitance. Capacity can be accurately predicted and controlled. In one embodiment of the present invention, a support layer having a main surface (for example, Si substrate 30), a lower electrode that overlaps the main surface of the support layer, and a layer of a material having a high dielectric constant that overlaps the upper surface of the lower electrode (for example, BST 44) and a microelectronic circuit structure. The lower electrode is a barrier layer (eg Ti N 36) and a non-reactive layer (eg Pt 42). |