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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G02F1-1365
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L49-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G02F1-136
filingDate 1993-04-23-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2cafb77867886fc5ffd22f91139b5708
publicationDate 1994-11-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H06308539-A
titleOfInvention Matrix array substrate manufacturing method
abstract (57) [Summary] [Object] To provide a method for manufacturing a matrix array substrate that reduces wiring resistance without impairing MIM element characteristics. [Structure] A low resistance first metal layer 16 and a second metal layer 17 are laminated on a glass substrate 12 to form a thin film. The second metal layer 17 is patterned into a predetermined shape by a photolithography process. The first metal layer 16 and the second metal layer 17 Using the as a mask, patterning is performed by a photolithography process to form a first metal electrode 18. An oxide film 20, on the surface of the first and second metal layers 16 and 17 by anodic oxidation Insulators 22 are formed by forming 21 respectively. 3 for anodic oxidation % Ammonium tartrate aqueous solution and ethylene glycol are used to adjust the pH to 6.5 to 7.5. A thin film of a third metal layer is formed on the surfaces of the oxide films 20 and 21, and a second metal electrode 24 is formed by patterning by a photolithography process to complete the switching element 14.
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priorityDate 1993-04-23-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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