http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H04199656-A

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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-31
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-76
filingDate 1990-11-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a746f5f47e48ab4081a1068d8b10b743
publicationDate 1992-07-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H04199656-A
titleOfInvention Manufacture of semiconductor device
abstract PURPOSE: To enable the upper recess of a groove to be flattened by a method wherein a low melting point glass film is formed on an insulating film provided onto the surface of semiconductor substrate where a dielectric is buried in a groove, and then the substrate is thermally treated. n CONSTITUTION: An insulating film 2 of silicon oxide is formed on the side wall of a groove provided onto a silicon semiconductor substrate 1, a dielectric 3 of polycrystalline silicon is filled into the groove where the insulating film 2 is formed, the insulating film 2 and the dielectric 3 formed outside the groove are removed by an etchback method, and the insulating film 2 of silicon oxide is formed on the surface of the silicon semiconductor substrate through a thermal oxidation method. Then, a PSG film 4 is formed on the surface of the insulating film 2 on the semiconductor substrate 1, and the substrate 1 is subjected to a reflow treatment in an atmosphere of nitrogen. By this setup, the PSG film 4 formed on the insulating film 2 is laid in the upper recess of the dielectric 3 buried in the groove, so that a recess formed on the top of the dielectric 3 clan be flattened. n COPYRIGHT: (C)1992,JPO&Japio
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priorityDate 1990-11-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 20.