http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H04137751-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_14c9ad767fb6d5e9dabfb770d4e82252 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C04B2111-00844 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C04B41-009 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C04B41-91 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76804 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C04B41-5346 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31116 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-311 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C04B41-53 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-522 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3065 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C04B41-91 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-302 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate | 1990-12-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6032a2d8c4c661daaf07a3e9bce60483 |
| publicationDate | 1992-05-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-H04137751-A |
| titleOfInvention | Forming method for via hole |
| abstract | PURPOSE: To form an accurate via hole by performing plasma etching through a photoresist pattern, provided on the silicon nitride layer of a double-layer dielectric forming the silicon nitride layer on a silicon oxide layer. n CONSTITUTION: In order to form a via on the double dielectric, composed of an SiO layer 18 formed on integrated circuit substrates 12 and 14 and an SiN layer 20 formed on it, a photoresist layer 22 is formed on the SiN layer 20, and subsequently the resist pattern of a via hole 10 is formed. Then, the SiN and SiO layers are etched through the via hole on the resist layer, and the via hole is formed on the double-layer dielectric. For the etching of the SiN layer, plasma for selectively etching SiN is used rather than the SiO layer. After the SiN layer has been etched, the via hole is extended through the SiO layer to the upper surface of a metal wire by selective plasma etching to metal, and a metallization layer is deposited on the dielectric, while including the inside of the via hole. Thus, formation for the via hole can be improved. n COPYRIGHT: (C)1992,JPO |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2006523428-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2010238988-A |
| priorityDate | 1990-01-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 28.