http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H03104181-A

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filingDate 1989-08-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7f24d8e7f669bb5eef6c6a429636a607
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publicationDate 1991-05-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H03104181-A
titleOfInvention Etching method for mirror facet for iii and iv compound semiconductor structure and forming method for etching mask
abstract PURPOSE: To provide a high-quality mask for an IBE treatment by using a master sandwiching an etching dielectric material layer between resist layers, removing the intermediate layer before etching, and making the lower resist of high etching resistance into only one mask. n CONSTITUTION: A multilayer GaAs/AlGaAs layer body structure 11 completing mirror facet etching preparation is covered with the mask of three layers of hard bake resist/amorphous SiO 2 /prebaked resist and patterned on upper resist PRtop and a mirror groove is formed. Next, RIE is performed in the exposed part of an SiO 2 layer in CF 4 plasma, the exposed part of a lower resist layer PRbot is etched by switching into O 2 , and at the same time, the PRtop is removed as well. By switching it to CF again, the remaining part of the SiO layer is removed. Next, etching is performed by a high vacuum CAIBE device, and an etching groove 19 is provided in the deep part of a lower clad layer in laser structure. Finally, the remaining PRbot is removed and washed in O 2 plasma, and etching of a mirror facet 20 in III and V compound semiconductor structure is completed. n COPYRIGHT: (C)1991,JPO
priorityDate 1988-09-12-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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