| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y99-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S438-981
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823462
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S977-936 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823468
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-82385
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823857
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0883
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42364
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-82345 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8244
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8246
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-112
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-822
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-413
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-00 |
| filingDate |
2012-04-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2013-10-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2013-10-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-5325317-B2 |
| titleOfInvention |
Semiconductor integrated circuit device |
| abstract |
The present invention is drawn to a semiconductor integrated circuit device employing on the same silicon substrate a plurality of kinds of MOS transistors different in magnitude of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of two power supply units. The control circuit is responsive to receipt of a control signal supplied thereto for controlling the flow of a current either between the source and gate or between the drain and gate of the tunnel-current increased MOS transistor for use with the main circuit in such a way that the current flow is selectively permitted during certain time period and that it is inhibited during another period. <IMAGE> |
| priorityDate |
1996-04-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |