| abstract |
Provided is a semiconductor device which is suitable for miniaturization and has high reliability and improved operation speed. In a semiconductor device, a memory cell having first to c-th (c is a natural number of 2 or more) sub-memory cells (j is a natural number from 1 to c) is provided, and a j-th sub-memory cell is provided. Has a first transistor Ta_j, a second transistor Tb_j, and a capacitor Ca_j. The first semiconductor layer included in the first transistor and the second semiconductor layer included in the second transistor include an oxide semiconductor. One of the terminals of the capacitor is electrically connected to a gate electrode 203j included in the second transistor, and the gate electrode included in the second transistor is connected to a source electrode or a drain electrode 104j_a or 104j_b included in the first transistor. The j-th sub-memory cell is electrically connected to one of the sub-memory cells, and the j-th sub-memory cell is arranged on the (j-1) -th sub-memory cell when j ≧ 2. [Selection diagram] FIG. |