| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823814
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823807
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823885
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-82385 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7827
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66666
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823412
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823487
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823456
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823807
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823468
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-82385
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-092 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate |
2017-06-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2019-07-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2019519928-A |
| titleOfInvention |
Semiconductor device and method of forming the same |
| abstract |
A vertical FET device having a plurality of channel lengths is provided. A semiconductor device includes a first source / drain region provided in a semiconductor substrate, a second source / drain region provided in the semiconductor substrate, and a lower spacer provided in the first source / drain region. And a lower spacer provided in the second source / drain region. A first gate stack having a first length is provided in the first source / drain region. The second source / drain region is provided with a second gate stack having a second length, the first length being shorter than the second length. An upper spacer is provided on the first gate stack and an upper spacer is provided on the second gate stack. [Selected figure] Figure 33 |
| priorityDate |
2016-06-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |