| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0f705f295f4ba571f5311e5ef1b57807 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2201-09227
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2201-099
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2203-072
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2201-096
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2203-1572
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2201-09563
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2203-107
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2201-09827
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2201-09727 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K1-0298
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-4644
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-422
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K1-0373
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-4652
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K1-145
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K1-115
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-06 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-46
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-12 |
| filingDate |
2017-10-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e386e721935f721034dbfb7fa4df091d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d72e9fbb19ba2bbf31d0e1c7856da0b6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_66e83285b1d570da31de46e85ef82c26 |
| publicationDate |
2019-05-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2019079900-A |
| titleOfInvention |
Printed wiring board |
| abstract |
PROBLEM TO BE SOLVED: To provide a printed wiring board having high mounting reliability. A printed wiring board according to an embodiment comprises a core substrate having a first conductor layer 34F and a second conductor layer 34S and a build substrate laminated on the core substrate. It has an upper layer Bu1 and Bu2. The buildup layers Bu1 and Bu2 have an inner conductor layer and an outermost conductor layer. The conductor circuit forming each conductor layer has a base angle, and the base angle of the conductor circuit forming the at least one inner conductor layer is larger than the base angle of the conductor circuit forming the first conductor layer. [Selected figure] Figure 2 |
| priorityDate |
2017-10-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |