| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B23K2101-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B23K2103-56 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3171
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B23K26-0624
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B23K26-57
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B23K26-53
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-82
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-268
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B23K26-0006
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B23K26-50 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-301
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B23K26-364
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B23K26-351 |
| filingDate |
2014-09-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2016-12-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2016539497-A |
| titleOfInvention |
Maskless hybrid laser scribing and plasma etching wafer dicing |
| abstract |
Maskless hybrid laser scribing and plasma etching wafer dicing processes are described. In one embodiment, a method of dicing a semiconductor wafer having a front surface overlaid with a plurality of integrated circuits, having a passivation layer disposed therebetween, and covering a metal pillar / solder bump pair of the integrated circuit is disclosed. Laser scribing of the passivation layer without the use of a mask layer. The method also includes plasma etching the semiconductor wafer with a scribe line to singulate the integrated circuit, and the passivation layer protects the integrated circuit during at least a portion of the plasma etch. The method also includes thinning the passivation layer to partially expose the metal pillar / solder bump pairs of the integrated circuit. [Selection] Figure 3D |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2019169686-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111656491-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-7267259-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10910270-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20200115901-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-102405460-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20220000462-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-102227858-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2019189173-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-WO2019189173-A1 |
| priorityDate |
2013-10-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |