http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2016186664-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5d7576285d411d00c697e07270d2814a |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7869 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0267 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-94 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78666 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C19-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3611 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3677 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C27-04 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G02F1-133 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-20 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-36 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G02F1-1368 |
| filingDate | 2016-07-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_30ce2918ee5323e5c67a768b80254eae |
| publicationDate | 2016-10-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2016186664-A |
| titleOfInvention | Electro-optic device |
| abstract | An electro-optical device that can efficiently use a region of a gate line driving circuit and can prevent a decrease (rise delay) of a rising speed of a gate line selection signal. A gate line driving circuit includes an odd driver that drives an odd row of a plurality of gate lines and an even driver that drives an even row. Each of the unit shift registers SR of the odd-numbered and even-numbered drivers 30a and 30b receives the selection signal Gk-2 of the previous two rows and activates its own selection signal Gk with a delay of two horizontal periods. The start pulse SP1 of the even driver 30b is delayed in phase by one horizontal period from the start pulse SP2 of the odd driver 30a. Each of the unit shift registers SR includes a first transistor Q1 that supplies a clock signal to an output terminal, and a second transistor Q2 that discharges the output terminal. The first transistor Q1 and the second transistor Q2 are oxide semiconductors. It is formed by. [Selection] Figure 3 |
| priorityDate | 2009-02-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 50.