| abstract |
A high-speed operation of an eDRAM is realized. An eDRAM is connected to a gate electrode G1 serving as a word line WL, a selection MISFET (TR1) having a source region SR1 and a drain region DR1, a source plug electrode PLGS connected to the source region SR1, and a drain region DR1. Drain plug electrode PLGD. The eDRAM is further formed on the capacitor plug electrode PLGC connected to the drain plug electrode PLGD, the bit line BL connected to the source plug electrode PLGS, the stopper film STP1 covering the bit line BL, and the stopper film STP1. The capacitor element CON includes the first electrode EL1, the dielectric film CINS, and the second electrode EL2. The first electrode EL1 is connected to the capacitor plug electrode PLGC, and the height of the capacitor plug electrode PLGC is equal to the height of the bit line BL. [Selection] Figure 3 |