| abstract |
A semiconductor device capable of adjusting the timing of a clock signal is provided. Alternatively, a high-quality semiconductor device or the like is provided. A circuit including a first transistor, a circuit including a second transistor, a channel of the first transistor includes an oxide semiconductor layer, and the first transistor includes a first transistor and a drain formed from one of a source and a drain of the first transistor. 1 is input, the other of the source and the drain of the first transistor is electrically connected to the gate of the second transistor, the first clock signal is input to the circuit, and the circuit receives the second clock signal. Is provided, and the timing of the second clock signal is different from that of the first clock signal. [Selection] Figure 1 |