| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_986d0ab29fa7910a46cd21a12d682fe4 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-517 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76838
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28176
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-268
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28008
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823871
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823842 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-49
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-316
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-417
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-522 |
| filingDate |
2013-12-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_eba705b3c9a87736b5f4bc45dd57db97
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f003c64a76a35fe7e815a16ba0e1347a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1b5f6dc71608c5020eab930608fc0fc4 |
| publicationDate |
2014-08-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2014146789-A |
| titleOfInvention |
Method for adjusting the effective work function of a gate structure in a semiconductor device |
| abstract |
A method for adjusting an effective work function of a gate structure in a semiconductor device is provided. The gate structure includes a metal layer and a high-k dielectric layer that separates the metal layer from an active layer of a semiconductor device. The wiring structure includes a laminate including at least the premetal dielectric layer 3, the premetal dielectric layer 3 has a metal-filled connection via connected to the gate structure through the premetal dielectric layer 3, and the wiring structure is an upper exposed metal. It has part 7. At least a portion of the upper exposed metal portion 7 is exposed to the plasma 5 under predetermined exposure conditions to adjust the effective work function of the gate structure. [Selection] Figure 1 |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9941376-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10998415-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-101740132-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10522640-B2 |
| priorityDate |
2012-12-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |