| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5e5c121269689cbab9b3a4548b15caf3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a0cf068c80e0b2c11156bf3554e24189 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32139
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10K10-491 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-49
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-41 |
| filingDate |
2012-02-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0d875fac75a64757d2e7f14db1ad647a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c7598791a764b5e2d88d6a704ca39b28 |
| publicationDate |
2013-08-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2013165175-A |
| titleOfInvention |
Thin film transistor having three-dimensional structure and manufacturing method thereof |
| abstract |
A thin film transistor having a structure in which a semiconductor layer is provided along a side wall surface in a vertical direction with respect to a main surface of a substrate, and a parasitic capacitance between a gate electrode and a source and drain electrode is reduced to a minimum. provide. An insulating substrate, a stepped structure having a side wall surface that is vertical to the main surface, and a gate provided along the side wall surface. An electrode layer 3; a gate insulator layer 4 provided so as to cover the gate electrode layer; a semiconductor layer 5 provided in a region along at least the side wall surface on the gate insulator layer; And a source electrode 6 disposed in one of the regions excluding the stepped structure portion on the substrate, and a drain electrode 7 disposed in the other, the source electrode and the drain electrode being located at the upper and lower end portions of the side wall surface Thus, each is formed so as to be connected to the semiconductor layer. [Selection] Figure 1A |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2016061571-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-110634390-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2018203181-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-7128809-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2014063962-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2015056498-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2016042707-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-WO2018203181-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10180364-B2 |
| priorityDate |
2012-02-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |