| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e5db580deca7130dbe51805c6c608b35 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10T428-31515
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-12105
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10T29-49126
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10T428-24463
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10T428-12993
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01029
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10T29-49156
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10T29-49155
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10T428-24355
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10T29-49165
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-15787
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-181
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-15788 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-19
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49816
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5389 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K1-02 |
| filingDate |
2011-08-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_735a5aa3ffeab2a3924cec63d5620c77
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dcf4340e8e1ff85fa9d0b70f31ac4cc2
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c2f0c7ab3e42971573e0f9d486857c69 |
| publicationDate |
2013-03-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2013048195-A |
| titleOfInvention |
Wiring structure and manufacturing method thereof, electronic device and manufacturing method thereof |
| abstract |
A highly reliable wiring structure and a manufacturing method thereof, and an electronic device having the wiring structure and a manufacturing method thereof are provided. A semiconductor chip is embedded in a substrate, and an upper surface of an electrode of the chip is exposed from the substrate. An insulating film 16 formed on the substrate, a plurality of wirings 22 connected to the chip electrodes and vias 15 formed on the insulating film, and the top surface of the insulating film in a region between the plurality of wirings is formed to form a recess 17. And an induction layer 24 that induces diffusion of constituent atoms of the wiring. [Selection] Figure 1 |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2016525274-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2017224642-A |
| priorityDate |
2011-08-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |