| abstract |
A semiconductor device including a silicide layer having an interconnect structure and a power MOSFET including a low profile bump and preventing a short circuit between bumps, and a manufacturing method thereof. A source region 160 and a drain region 170 are provided on a substrate, and a silicide layer 174 is disposed on the source region and the drain region. A first interconnect layer 194 is formed on the silicide layer, and a first runner 196 connected to the source region and a second runner 198 connected to the drain region are disposed. A second interconnect layer 214 is formed on the first interconnect layer, and a third runner 216 connected to the first runner and a fourth runner 218 connected to the second runner. Including. A third interconnect layer 234 is formed, and the source pad 236 and the source bump 240 are electrically connected. [Selection] Figure 4t |