| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d80f1040809503e54509c871ba828f75 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31111 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-67178
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-67184
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-6719
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0217
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32139
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02274
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0337
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-308
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-30604
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3213 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3213
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3065 |
| filingDate |
2011-02-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ad99986e1cdbf513d9be5f670bac23c6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_352e7bc57560deddcc3c3aff2b9805ee
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_73d9456f939b1cce9d6b8fbb86309809
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_73d9c90244581a46d9efe5ee922d4259 |
| publicationDate |
2012-09-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2012174891-A |
| titleOfInvention |
Pattern forming method and semiconductor device manufacturing method |
| abstract |
A mask for etching a film to be processed on a substrate is appropriately formed in a predetermined pattern in a low temperature environment where the temperature of the substrate is 100 ° C. or lower. An antireflection film 401 and a resist pattern 402 are formed on a processing target film 400 of a wafer W (FIG. 10A). The resist pattern 402 is trimmed and the antireflection film 401 is etched (FIG. 10B). Plasma processing is performed in a state where the temperature of the wafer W is maintained at 100 ° C. or less, and a silicon nitride film 404 having a film stress of 100 MPa or less is formed on the resist pattern 402 and the antireflection film pattern 403 (FIG. 10 ( c)). The silicon nitride film 404 is etched, the resist pattern 402 and the antireflection film pattern 403 are removed, and a silicon nitride film pattern 405 is formed on the processing target film 400 (FIG. 10D). [Selection] Figure 10 |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-7142611-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2019197903-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2017503359-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2020184337-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-7318174-B2 |
| priorityDate |
2011-02-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |