Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9a9aad45e5465bd5d3e7e503b2b16c65 |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4966 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-495 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28079 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28088 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28518 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6659 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-665 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-517 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-49 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
filingDate |
2010-01-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4272aefff65da0a72a659574b2ea5d44 |
publicationDate |
2011-07-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
JP-2011146465-A |
titleOfInvention |
Semiconductor device and manufacturing method thereof |
abstract |
The present invention provides a manufacturing method capable of avoiding a dummy gate electrode cueing process by CMP and a metal gate electrode forming process by CMP. A step of selectively forming silicon films (25S, 25D) on silicide films (24S, 24D), a step of forming a recess (23V) exposing the surface of the silicon substrate between sidewall insulating films (23WA, 23WB); A step of forming a dielectric film so as to continuously cover the surfaces of the sidewall insulating films 23WA and 23WB and the exposed silicon substrate surface, and a conductive film containing a metal or a conductive metal nitride on the silicon substrate; A step of filling 23V through a dielectric film, and a step of etching back the conductive film to form a gate electrode filling the recess 23V through the dielectric film between the sidewall insulating films 23WA and 23WB. And including. [Selection] Figure 2E |
isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9741855-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2014107546-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9768300-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2013524529-A |
priorityDate |
2010-01-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |