| abstract |
An electronic component device manufacturing method capable of reducing the mounting area of an electronic component and mounting the electronic component with high parallelism is provided. A silicon substrate, a recess provided on the upper surface thereof, a through hole TH formed through the silicon substrate on a bottom surface of the recess, and an insulating layer formed on the silicon substrate. 14, a lower metal part 22 formed from the lower part in the through hole TH to the middle in its height direction, and a connecting metal member 26 (indium layer) formed on the lower metal part 22 in the through hole TH ) And a step of preparing a wiring board 1 having a through electrode 20 and an electronic component 40 having a terminal metal member 42 (gold bump) on the lower surface side, and a heating atmosphere. And softening the connecting metal member 26 and piercing the connecting metal member 26 to connect the terminal metal member 42 of the electronic component 40. [Selection] Figure 9 |