| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-13025
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06513
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06541
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16225
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05573
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06527
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-00014 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-063
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5286
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-02 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-52
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-07
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-822
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-04 |
| filingDate |
2009-06-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8be858a2028428b9b6aeb8868e031b3e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_11e48418cce205531435e5a3a87b7e61
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_42b693bd49abb422a4dc366fee4debd1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ba20b57b1556b3d4fd030945461b71c3 |
| publicationDate |
2010-01-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2010016377-A |
| titleOfInvention |
Multi-die integrated circuit device and method |
| abstract |
Provided is a device capable of efficiently arranging contact pads of through silicon vias when a plurality of dies are stacked as a three-dimensional integrated circuit package. In an integrated circuit including a first die coupled to a second die, such as a memory die, a plurality of through silicon vias TSV are provided to penetrate the second die and supply a power reference to the first die. The plurality of through silicon vias can be rearranged laterally without interfering with the plurality of circuit sections MS of the second die. [Selection] Figure 3 |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-101932660-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2014057065-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9087822-B2 |
| priorityDate |
2008-06-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |