http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2009539267-A

Outgoing Links

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classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32137
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10K99-00
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81C1-00571
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3065
filingDate 2007-05-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationDate 2009-11-12-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2009539267-A
titleOfInvention Method for minimizing mask undercuts and notches in plasma processing systems
abstract A method of etching a silicon layer of a substrate disposed on a bottom electrode in a plasma processing chamber. The method includes performing a main etch step until at least 70 percent of the silicon layer is etched. The method further includes an overetching step that includes first, second, and third processing steps. The first processing prescription is used in the first processing step, the second processing prescription is used in the second processing step, and the third processing prescription is used in the third processing step. The second process recipe uses a second bottom bias voltage level applied to the bottom electrode, which is the first bottom bias voltage level used in the first process recipe and the third bottom bias voltage used in the third process recipe. Higher than level. The first, second and third processing steps are alternately performed a plurality of times until the silicon layer is completely etched. [Selection] Figure 2
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2015511766-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2017208548-A
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priorityDate 2006-05-30-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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Total number of triples: 26.