| abstract |
A small surface-mount package in which a power MOSFET or the like is sealed achieves a low on-resistance. Two silicon chips 3H and 3L are sealed inside a mold resin 2. On one side of the mold resin 2, three source leads 4S2 and one gate lead 4G2 are arranged. The three source leads 4S2 are connected to each other inside the mold resin 2, and the connected portion and the source pad 7 of the silicon chip 3L are electrically connected via the two Al ribbons 10. Yes. Further, the gate pad 8 of the silicon chip 3L is electrically connected to the gate lead 4G2 through one Au wire 11. [Selection] Figure 16 |