| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_294881271413951a95f284b588a68e66 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1037
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6659
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66628
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6653
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-26586
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66659
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7835 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8244 |
| filingDate |
2006-09-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4b411d1a52d54c9e69772a8303b9bd4f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fac171fc48c782d53657df0201f129d6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bdf4609867c5a6708e5a33cdf9ec25d7 |
| publicationDate |
2008-03-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2008060497-A |
| titleOfInvention |
Semiconductor device and manufacturing method of semiconductor device |
| abstract |
In a MOSFET, it is possible to achieve both suppression of a short channel effect and improvement in mobility. A semiconductor region having a first semiconductor surface and a second semiconductor surface that is connected to the first semiconductor surface and is inclined with respect to the first semiconductor surface, and first and second semiconductor surfaces. , 12 on the boundary between the first and second semiconductor surfaces 11, 12 via the gate insulating film 21, and in the gate electrode 22 and the first semiconductor surface 11 with the gate insulating film 21 interposed therebetween A source impurity region 23 formed in the semiconductor region 10 so as to overlap, a drain impurity region 24 provided in at least the semiconductor region 10 immediately below the second semiconductor surface 12, and a junction between the drain impurity region 24 and the semiconductor region 10 The interface Jd is formed closer to the boundary B between the first and second semiconductor surfaces 11 and 12 than the junction interface Js between the source impurity region 23 and the semiconductor region 10. [Selection] Figure 1 |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-115083918-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-115083918-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2008177278-A |
| priorityDate |
2006-09-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |