| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_294881271413951a95f284b588a68e66 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53295
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2221-1089
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76808
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76867
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76864
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76873
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53238
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76831
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76843
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76844 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-52
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205 |
| filingDate |
2006-08-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6207b1cbd403b15597fc82bfd4bcf9ea
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d167cc576a1fb355456d99155c5794c0 |
| publicationDate |
2008-02-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2008047719-A |
| titleOfInvention |
Manufacturing method of semiconductor device |
| abstract |
A method of manufacturing a semiconductor device that prevents peeling of a conductive layer while suppressing a load on a plating process, improves uniformity of embedding of the conductive layer in a substrate surface, and suppresses an increase in wiring resistance. I will provide a. First, a step of forming a wiring trench 16 in an interlayer insulating film 15 provided on a substrate 11 is performed. Next, a process of forming a plating seed layer 17 in which an alloy layer 17a made of a CuMn alloy and a conductive layer 17b made of pure Cu are stacked in this order while covering the inner wall of the wiring groove 16 is performed. Next, a step of embedding a conductive layer 18 made of pure Cu in the wiring groove 16 provided with the plating seed layer 17 is performed by plating. Thereafter, heat treatment is performed to cause Mn in the alloy layer 17a to react with the constituent components of the interlayer insulating films 12 and 15, and Mn having a Cu diffusion barrier property at the interface between the alloy layer 17a and the interlayer insulating films 12 and 15. A method of manufacturing a semiconductor device comprising performing a step of forming a self-forming barrier film 19 made of a compound. [Selection] Figure 1 |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2008124275-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9112004-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8531033-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8765602-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8653663-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2010007951-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2010021490-A |
| priorityDate |
2006-08-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |