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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786
filingDate 2006-03-17-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d910389c0eb7d05fd5027d80144d7eaa
publicationDate 2007-09-27-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2007250987-A
titleOfInvention Solid-state electronic device and manufacturing method thereof
abstract An object of the present invention is to reduce an off-current and improve a subthreshold coefficient in a solid-state electronic device (transistor). A channel layer having a gate electrode 3 to which a control voltage is applied, a source electrode 4 and a drain electrode 5 whose conduction state is controlled by the control voltage, and generating a channel between the source electrode and the drain electrode 1 and a gate insulating film 2 that is provided between the gate electrode and the channel layer and is made of a dielectric material having a large equivalent relative dielectric constant. And the gate insulating film 2 are planarized so that the RMS value is 1 nm or less. [Selection] Figure 10
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priorityDate 2006-03-17-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 38.